This invention relates to computer systems adapted to use the Peripheral Component Interface (PCI) bus and, more specifically, to a computer system employing a PCI adapter card containing programmable read only memory.
As shown in FIG. 1, a computer system 100 configured to use the PCI architecture includes a host processor 105, memory 110, a Processor-PCI bridge circuit 115, and one or more PCI devices 120. Internal host processor buses 125 are used to communicate information among the computer system's different elements. The PCI bus 130 is used to communicate information between the processor 105 or memory 110 and the PCI device 120. The computer system 100 could, for example, be one element in a larger system comprising video displays, keyboards, print devices, network connections, and graphical input/output devices.
Illustrative host processors 105 include the 80X86 family of processors and the PENTIUM and PENTIUM PRO processors, all manufactured by Intel Corporation. Memory 110 typically includes random access memory (RAM), read only memory (ROM), and at least one type of permanent storage device such as an electromagnetic tape, electromagnetic fixed and/or floppy disk, and/or an optical disk unit. Typical PCI devices include ethernet controller cards, disk array controller cards, video controller cards, and Small Computer System Interface (SCSI) bus adapter cards.
A PCI device 120 is frequently embodied on a separate PCI card (referred to as a PCI adapter card or, more simply, adapter card) that plugs into the computer system's PCI bus 130. As shown in FIG. 2, an adapter card 120 may itself have a central processing unit (CPU) 200, programmable ROM (PROM) 205, RAM 210, and a connector 215 through which signals are transmitted (via the adapter's local bus 220) to and from a host processor 105 (not shown in FIG. 2).
The terms "host processor" and "CPU" are adopted here as a convenient means to distinguish the processor (105) controlling the host computer system (100) and the processor (200) controlling the adapter card (120). In fact, either processor may be implemented with any suitable microprocessor such as the 80X86, PENTIUM or PENTIUM PRO processors from Intel Corporation, or the 680X0 or POWER PC processors from Motorola Corporation. Further, the host processor 105 and CPU 200 can be configured to execute any convenient operating system, for example, DOS or WINDOWS 95 from Microsoft Corporation, or UNIX.
When a computer system 100 having a PCI bus architecture first powers up, the host processor 105 locates the PCI bus 130 and determines the existence and type of any PCI device present. A PCI device 120 is nonresponsive to memory and input/output (I/O) space addressing on the PCI bus 130 until the configuration space of the PCI device is programmed by the host processor 105.
Following detection of a PCI device, the host processor 105 allocates memory and I/O space for the PCI device and, using the PCI standard's defined configuration protocol, programs the configuration space of the PCI device with the addresses of the memory and I/O space allocated to the PCI device. Following configuration the PCI device may be assigned memory and/or I/O space and can then respond to memory and I/O space bus cycles accordingly.
Many adapter cards use ROM that is capable of being reprogrammed. This type of memory is known as programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), or FLASH EEPROM. The ability of the adapter card 120 to reprogram itself facilitates upgrading the card's operation or correcting errors ("bugs") in the card's operational software (stored in PROM 200).
As shown in FIG. 3, adapter PROM 205 can be divided into a boot block 300 and an operational code block 305. The boot block 300 contains code that is needed to initialize the adapter's CPU 200, and reprogram the PROM's operational code block 305. The set of instructions executed by the adapter's CPU 200 to reprogram the PROM 205 is referred to as PROXY code. The operational code block 305 contains the code that implements the adapter's function.
During adapter initialization the CPU 200 executes the instructions stored in the boot block 300, see FIG. 4. First the CPU interrogates its RAM 400 and sets the adapter's PCI configuration register(s) 405 in accordance with the PCI standard. Next, the CPU checks to see if the PROM's content is intact 410. This is typically done via a cyclic redundancy code (CRC) check. If the PROM's CRC test passes, the adapter's operational code 305 is copied into RAM 415 after which the CPU idles until commanded by the processor 420. If the CRC test fails at step 410, the CPU copies the boot block's communication and reprogramming (PROXY) code into RAM 425 and then waits for the host processor 105 to send it new program code 430, i.e., a new set of operational instructions. When the new instructions are received from the host processor, the adapter replaces the PROM's operational code block 305 with the newly downloaded instructions 435 in accordance with the boot block's reprogramming code. PROM reprogramming is now complete and the adapter can be reset in preparation for executing the newly stored instructions.
During reprogramming, if an error appears in the PROM's boot block 300 where the reprogramming or communication code is stored, the adapter cannot be reprogrammed in the field by the adapter's end-user/purchaser. Should an image (the code contained in the PROM's 205 operational code block 305) be downloaded and fail to function properly, the end-user may have no way/capability to reprogram the device. Should power be interrupted during a reprogramming event (see FIG. 4, step 435), the code image downloaded from the host processor may be so corrupted that the adapter card cannot initialize itself.